Qualcomm Off-Campus 2025 | Engineer | Bangalore| Apply Now

Skills:

• 2-10 yrs experience in Physical Design and timing signoff for high speed cores.
• Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.
• Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 2+ years of experience in IC design.
• Experience in leading block level or chip level Physical Design, STA and PDN activities.
• Work independently in the areas of RTL to GDSII implementation.
• Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
• Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
• Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
• Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.
• Strong problem-solving skills.

Qualification: 

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  OR
  
• Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  OR
  
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field